省電力モードで設定可能なXENVは上記キーのみになります。 PLL2はDRAM/周辺デバイスの供給されるクロックになりますので、 これを残しておく必要があります。 クロックの設定の仕方は下記参照ください。 各周辺デバイス毎にOn/Offするというような制御はできません。

The "pll0" and "pll2" keys control the PLL0 and PLL2, respectively. On SMP8674, PLL0 is not even used. PLL2 is used as the source clock for USB (cd2), SATA (cd3), SDIO (cd6), and the various audio and video clocks, and the clean dividers are used as the source clocks for some peripherals and the AV engines. In standby mode, it makes sense to program PLL2 to 0, to stop the PLL and save power that way. In power-saving mode, you might want to leave some of those peripherals running, so you wouldn't shut off PLL2.

For "pll" key, the formula is: PLLx_freq = (27000000 * (N+1)) / *1 Where N is PLLx[7:0], M is PLLx[22:16], and K is PLLx[15:13].

So, if PLL2=0x0101203b: N=0x3b M=1 K=1 Thus: PLL2_freq = (27000000 * (0x3b+1)) / *2 = 405000000 = 405 MHz For "mt3_hs" keys, first value is the PLL 1 value, second value is for mux, third is for premux. The rest are all DRAM0/1 configurations. For "mux" value, [0] is for S flag. [11:8] is for Ratio. [27:24] is for dpc. The S flag selects whether XTAL_IN (0=power up value) or PLL_SYSCLK (1) is fed into the dividers. Ratio controls the dividers ratio as follows:

Ratio | System Clock | CPU clock | VDEC DSP clock 0000 | ÷ 2 | ÷ 2 | ÷ 2 0001 | ÷ 4 | ÷ 2 | ÷ 4 0010 | ÷ 3 | ÷ 2 | ÷ 3 0011 | ÷ 3 | ÷ 3 | ÷ 3 The dpc field indicates how many gate delays are needed to do 1 system clock cycle (Read only). It can be used to verify the PVT characteristics.

For "premux" value, [1:0] is for sys, [10:8] is for cd, [20:16] is for duty. Two clocks CD_CLK and PLL_SYSCLK can be derived from PLLO~3 as follows: sys (PLL_SYSCLK) : 0=NA, 1=PLL1_0, 2=PLL2_0, 3=NA cd (CD_CLK) : 0=NA, 1=Off, 2=PLL1_0, 3=PLL1_1, 4=PLL2_0, 5=PLL2_1, 6=NA, 7=NA

The field “duty” controls the duty cycle of the PLL_SYSCLK: ? Value 0 means 50%. Values 1..15 increase the low time. ? Value 16 means 50%. Values 16..31 increase the high time. ? Default value is 0. Note: Changing the sys or duty fields may create glitches on PLL_SYSCLK. This should be done only when the system clock is derived from XTAL_IN (not PLL_SYSCLK). Similarly, changing the cd field may create glitches on CD_CLK. This should be done only when the clean dividers are not in use


You shouldn't use any of the other values for DRAM settings, they don't apply to the SMP8674, which uses DDR3, not DDR2.

The other "standby" ZXENV keys are not used for the SMP8674, because those are related to DDR2 settings for low frequency or standby mode, and SMP8674 uses DDR3


  

*1 M+1)*(2^K
*2 1+1)*(2^1

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Last-modified: 2014-04-15 (火) 19:25:12 (1701d)